Svc out

ABSTRACT

1. A MULTITRACK-RECORD SYSTEM FOR PROCESSING DIGITAL DATA SIGNALS WITH RECORDING CIRCUITS AND READ-BACK CIRCUITS HAVING HEAD-TRACKING CAPABILITIES AND FOR BEING IN OPERATIVE ASSOCIATION WITH A RECORD MEDIA RELATIVELY MOVABLE WITH RESPECT TO MAGNETIC TRANSDUCERS IN EITHER DIRECTION ALONG A GIVEN PATH, A BYTE BEING A GROUP OF SIGNALS HAVING ONE SIGNAL RESPECTIVELY ASSOCIATED WITH A TRACK, THE IMPROVEMENT INCLUDING IN COMBINATION: DATA MEANS FOR SELECTIVELY ESTABLISHING DIGITAL DATA SIGNAL-PROCESSING OPERATIONS IN SAID CIRCUITS, SAID OPERATIONS PROCESSING DIGITALS SIGNALS TO AND FROM SAID RECORD MEDIA, SAID SIGNALS EXHIBITING PREDETERMINED FREQUENCY CHARACTERISTICS, RESYNC MEANS OPERATIVELY COUPLED TO SAID CIRCUITS FOR SELECTIVELY ESTABLISHING RESYNC RSIGNAL PROCESSING OPERATIONS IN SAID CIRCUITS FOR PROCESSING RESYNC SIGNALS HAVING FREQUENCY CHARACTERISTICS WITHIN SAID PREDETERMINED FREQUENCY CHARACTERISTICS, CONTROL MEANS INCLUDING CYCLING MEANS AND CAPABLE OF INTERRUPTING SAID DATA MEANS OPERABLE FOR INTERLEAVING AN OPERATION BY SAID RESYNC MEANS, SAID RESYNC MEANS BEING RESPONSIVE TO SAID INTERRUPTION TO EFFECT PROCESSING OF SAID RESYNC SIGNALS, SAID RESYNC SIGNALS EXHIBITING AT LEAST ONE UNIQUE SIGNAL CHARACTERISTIC NOT FOUND IN SAID DIGITAL SIGNALS FOR INDICATING POSITION OF SAID RESYNC SIGNALS ON SAID MEDIA, AND SAID DATA MEANS INCLUDING MEANS FOR DETECTING AND INDICATING POSITIONAL RELATIONSHIP BETWEEN SAID TRACKS BY SAID RESYNC SIGNALS AND INCLUDING FURTHER MEANS FOR ESTABLISHING SAID PREDETERMINED FREQUENCY RELATION BETWEEN SAID RESYNC SIGNALS AND SAID DATA MEANS.

J. w. IRWIN Re. 28, 265

INTRARECORD RESYNCHRONIZATION IN DIGITAL'RECORDING SYSTEMS Due. 10, 197411 Sheets-Sheet 3 Original Filed Dec. 29, 1969 TRANSFER ONE BYTE TOWRITE CIRCUIT START WRITE MAKE ONE BYTE AVAILABLE WRITE INITIAL SYNCBURST SIGNAL TRANSFER ONE BYTE TO WRITE CIRCUIT TRANSFER ONE BYTE TOWRITE FIG. 3A

WRITE PREAMBLE CIRCUIT ALTER BYTE COUNT WRITE CHECK DICIT SET WRITE DATACYCLE D- 10, 1914 w, mwm Re. 28, 265

INTEL-RECORD RESYNCBROHIZATIOH I}! DIGITAL-RECORDING SYSTEMS OriginalFiled Dec. 29, 1969 11 Sheets-Sheet 4 FROM FIG. 51 STEP 14 T 111 an STOPCYCLE RESET WRlTE 011111 CYCLE 11111115 A? 1111111511 51cm I j 1 1 i 1 11 /89 1 1 ALTER 111m 1 BYTE cow 1 110111111;

L/ 1 1 1 I 1 1 1 1 111111 1 1 1 l i ljj ijjiiijjjj; r

\ r 1 1 1 11mm /80 1 1 1 1 5111c BURST I 1 1 1 $191111 1 I 1 1 92 1WRITE 1 I 1 POSTAMBLE l 1 1 1111511 1 ,(END 19 1 END 15 1 1 01111111 1 iI I 1 1 1 1 1 l t .I i 1 1 1 1 1 1 l STEP 65 Doc. 10, 1974 J. W. IRWINDETECT INTRARECORD HESYNCHRONIZATIOH IN DIGITAL-RECORDING SYSTEMSOriginal Filed Dec. 29, 1969 11 Sheets-Sheet 5 FIG. 4 BEGINNING orRECORD BLOCK ER'D'R'RE" FORWARD '2 5|GNAL5 1o9 ALTER BYTE coum MARKER5mm '2 YES YES TRANSFER 3%??? RR SEOUENCE- 1oe WAIT TWO 105x CLOCKCYCLES l REENTER READ SET SEOUENCE\ STEERING READ DATA M /mBYTAELTCEJEJNT READ RESYNC CYCLE (FIG. 5)

END OF DATA Dec. 10, 1974 J. w. mwm Re. 28, 265

INTRARECORD HESYNCHRONIZATIOH IN DIGITAL-RECORDING SYSTEMS OriginalFiled Doc. 29, 1969 11 Sheets-Sheet 6 END OF DATA FROM FIG.4,STEPS 140DR 112 I H6 T 125 RESET SET READ STEERING TEST LATCH FIG. 5

N0 N0 SIGNAL? FORWARD YES a TRACKS STEP R00 TD 0 RESTART TRAAADTTTNG YESR I STOP READ REDUEUE DEAD TRACK 1! REENTER READ SEQUENCE T0 FIG. 4,STEP 1D? Ba. 10, 1974 J. w. IRWIN Re. 28, 265

INTRARECORD RESYNCHHONIZA'I'ION IN DIGITAL-RECORDING SYSTEMS OriginalFiled Dec. 29, 1969 11 sheets sheat 7 BLUCK 221 ,220 DETECTEOQ 222INITIAL (m 2) 152 "A E AQ READ 259 (FIGS) RESET LE A 200 a FWD. 2

START READ RESYNC 205 T0 FIG.8

(E|r;.n* *JA} Z STEERING jA|-{M2 I OTC 33 139 WRITEI 2 CLOCK A 0 /38A140 #0 CHL. SVC. IN m1) 3A 11s READ DATA-1255 (FIG. a)

SET svom [194 as 1 W svc. m cumom 7 0 /5T svc. our END OF PREAMBLE 6 m,155 156 15 V WRITE I 144 246 BYTE DETECT Ego mom 3? COUNTER B 0 22222-438 a PM) 148 PADH START" EHFFIATQ-THALH'S 235126 /215 1 8 SIGNALS==wRnE ALL 0's TO WRITE FROM 1/0 cmcun 42 Dlt. 10, 1974 w, mwm Re. 28,Z65

INTRARECORD RESYNCHRONIZA'IION IN DIGITAL-RECORDING SYSTEMS OriginalFiled Dec. 29, 1969 11 Sheets-Sheet a 22 a? E; f

$15220 Em E 32% 22: 2:5} m1 g 5% Wm E; 552E 3% 2 2 5; m2 2 2 E; 3 2K 8a: o: T! a 532550 51 xx EE 1 525 $5 25% Ex 2 2% has, 1 a L: E Q 21 E wmm o 20 k V :35 E 2:2 .L g a: :58 wczu 6.5 PE; .21? mwv P5; to l 0 E E535 a 52: E Z

J. W. IRWIN Dec. 10, 1974 ll Sheets-Sheet 9 ig'inal F1106 D86. 29, 1969Q :30 2: :5 5Z2: 5:? s 02 mg m T E25 :2: E E5 5% E25: am 252m 3352: D2am @555 $222 :2: i am a: 22 E 525 E 2%: 2: Es an gm :5 ea 5 a 0; E 2 55E3 :2 a: z 2 2 Q5: 35: $2562 mac :2:

Due. 10, 1974 J. w. IRWIN Re. 28, 265

m'rammcoan nssmcnnomzuxonm DIGITAL-RECORDING SYSTEMS Original Filed Dec.29, 1969 11 Sheets-Sheet 11 EN SE 3% I N 2m :25 ma ll|||. L 3 1 552353252w 1? 5523255 2 2 a 2 295032 nseozm llllr aseolmvff zs Q2 mseolmffiasaoT NIIZZ::-w@ =s 232E coax:: :ii zzoccoaoo gc 522x25 s20lmvm zeolseolmqo$7 M; 235s: 2:::: :I: ;;OQQQQQQQQ QQ 522:5: oooooooo cooooooZMQmMIQZf QO 22:5: 5222 5225 c a Q Q Q Q Q Q Q Q 4; 522 25 22: as: 92E; QZEZE 25E 0? 0 m United States Patent 28,265 INTRARECORDRESYNCHRONIZATION IN DIGITAL-RECORDING SYSTEMS John W. Irwin, Loveland,Colo., assignor to International Business Machines Corporation, Armonk,N.Y. Original No. 3,641,534, dated Feb. 8, 1972, Ser. No. 888,766, Dec.29, 1969. Application for reissue Feb. 4, 1974, Ser. No. 439,480

Int. Cl. Gllb 5/02 US. Cl. 36050 59 Claims Matter enclosed in heavybrackets appears in the original patent but forms no part of this reismespecification; matter printed in italics indicates the additions made byreissue.

ABSTRACT OF THE DISCLOSURE In a block of recorded data,resynchronization signals are interleaved among sets of sub-blocks ofdigital data signals for enabling reestablishment of self-clocking in adead track. Resynchronization occurs within a block of recorded data. Ina multitrack system, requiring the dead track in the skew buffers (SKB)is accomplished by placing the dead track SKB position at maximumleading relationship to the most lagging active track. If data signalsfrom the previously dead track are received by SKB before the dead trackhas reached maximum lagging relationship, the previous dead track isactivated for normal operation. Otherwise, the dead track is returned todead-tracking status. The readout counter (ROC) of SKB controlsread-back operations and determines signal format on the record media.

BACKGROUND OF THE INVENTION The present invention relates to movingmagnetic media recording systems and, particularly, to a self-clockingresynchronization system and method for use within blocks ofmagnetically recorded data signals.

The design and method of operating magnetic record'- ing systems isusually a compromise between reliability and increasing data throughput.Users of magnetic recording systems often sacrifice throughput todecrease the number of permanent errors. Such reduction in permanenterrors in the recording system for a given amount of data to be recordedhas been accomplished by dividing the data into small blocks of recordedsignals. Since, in present-day tape systems, a minimum spacing isusually provided between successive blocks of data, such approach notonly reduces the available tape recording area in a given tape but alsoreduces the throughput of the system.

In higher density recording systems (1,000 bits per inch and more), itis practically a necessity that each track of data on a recording mediumbe characterized such that it can be self-clocking. The reason for thisarrangement is that the cell in such a recording system is extremelyshort along the length of the media. Without self-clocking, dataprobably could not be successfully recovered. For successfulself-clocking, it is desirable that the clock in the readback system besynchronized to the data as read from the tape every short distance oftravel of the tape. To facilitate such resynchronization, it isdesirable to have predetermined flux transitions occur in the recordingat least once during a short length of tape. This can be accomplishedeither by inserting synchronization transitions between small sets ofdata signals or by utilization of a storage code having suchtransitions. The characteristics of such clock-synchronizing signals aresuch that the phase of the clock can be maintained, but that thefrequency and phase-synchronizing and position-indicating 'icecomponents thereof are insufiicient to enable a clock that is out ofsynchronization to start proper operation.

The problems stated above are caused by present-day magnetic mediarecording systems having no facile method of resyncing within a block ofdata signals after a defect in the tape or lift-off has occurred; thatis, after a signal has been lost from a given track. Such magnetic mediarecording systems continue in a degraded mode of operation; that is,without data signals from the defective (dead) track, throughout theremainder of the record block. Therefore, it is highly desirable that amagnetic media system should be able to resync within a block of data.To date, this has not been practical because, when data is recorded,there is a randomness of the recorded signal in accordance withinformation represented. Such randomness does not have predictablefrequency and phase components nor precise position information such asto enable such resynchronization.

SUMMARY OF THE INVENTION It is the prime object of the present inventionto pro vide high-density digital data recording in blocks of data havinga capability of resynchronizing a dead track on-thefly within any blockof such data.

A recording system using the present invention includes recording a setof data signals, then recording a set of resynchronization signalshaving predetermined signal phase and frequency-synchronizing andposition-indicating components and repeating such recording steps untilall data in one block has been recorded. Marker signals may be used tomark the boundary between the synchronizing and data signals, especiallyif the resynchronization signals are a valid form of recorded data.

A block of such recorded data is usually characterized by a preamble setof synchronization signals, a marker signal, then alternate sets of datasignals, marker signals and resynchronization signals, and, finally, apostamble set of synchronization signals. The postamble enables readingthe data block in a reverse direction. Padding signals may be added toone of the sets of data signals within the block such that all sets ofdata signals have the same number of digit positions or the sameremainder when divided by the number of readout counter (ROC) states.The second method does not require padding in excess of the number ofROC states and therefore makes a more efficient use of the media. Markersignals may again mark the boundary between data signals and the paddingsignals within such sets of data signals.

A multitrack recording system usually has deskewing apparatus; that is,electronic circuitry capable of randomly receiving signals from amagnetic media wherein the signals from one track lead or lag signalsfrom another track. The deskewing apparatus realigns the data into bytesfor processing by other apparatus. According to a feature of the presentinvention, a dead track is resynchronized and requeued into thedeskewing apparatus by artificially making the dead track position in adeskewing apparatus at maximum leading position. As data from the trackbeing resynchronized is introduced into the deskewing apparatus,requeuing occurs. However, if the dead track position reaches maximumlagging position in the deskewing apparatus, the dead track may bereturned to dead-track status until the next set of synchronizingsignals is received. Then, resynchronization is again attempted. Theinterleaving of resynchronization signals with data signals within thedata block not only provides for automatic resynchronization but alsothe requeuing of a dead track in a read-back system.

In a broad aspect of the invention, any suitable synchronization signalmay be interleaved with data signals to enable the describedresynchronization. To reduce costs, it is preferred thatresynchronization signals interleaved with data signals have the samechracteristics and length as the preamble and postamble synchronizationsignals. Since many preambles and postambles are strings of ls or Us aspecific feature of the invention provides resynchronization signalswithin a block of data as a string or burst of 1 or 0 signals. Bursts ofany signal combinations may be used.

The present invention may be practiced either in a programmed generalpurpose machine (such as a microprogrammed machine), a completelyhardware-provided set v of sequences, or a combination of the two. Anexample of a suitable microprogrammed control unit is the IBM 2841microprogrammable control unit.

Another feature is the utilization of the deskewing counter (ROC) as acontrol counter in a recording system. Data addressing may beaccomplished with this feature. Formatting of recording is based on anintegral number of rotations (ROC cycles completely through all of itspossible signal states in each rotation) of the deskewing counter.Symmetrical formatting is preferred for enhancing bidirectional reading.This format preferably includes symmetrically recorded resync signals.In this regard, the number of processed signal bytes is tallied fordetermining the length of a set of signals. ROC may be a part of such acounter.

In one form of the invention, resynchronization is based upon detectionof resync signals written as bytes in plural tracks on the recordingmedia. The resync signal then has a length of not less than twice themaximum compensable skew in the recording system. When the resyn signalin each track provides track position information independent of similarsignals recorded in other tracks, the resync signal need not be suchlength. Requeuing of the previously dead track in the deskewingapparatus of the system may use those features of the present invention;for

example, making the dead track effectively appear as the most leadingtrack at the onset of resync attempts while the most lagging at theextreme end of an unsuccessful resync attempt.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified diagrammaticpresentation of a single track of data recorded in accordance with theteachings of the present invention. The illustrated format facilitiesreading in either direction and provides intrablock resynchronization ineither direction of reading.

FIG. 2 is a simplified block signal diagram of a magnetic tape systemutilizing the teachings of the present invention.

FIGS. 3A and 3B show a simplified program/hardware operation flow chartused to record a block of data in accordance with the teachings of thepresent invention and is used to describe the recording operation of theFIG. 2 illustrated apparatus. These figures are referred to generally asFIG. 3.

FIG. 4 is a simplified program/hardware operation flow chart of a readsequence used to read back and resynchronize a dead track in accordancewith the teachings of the present invention.

FIG. 5 is a simplified program/hardware operation flow chart showingdetailed read-back resynchronization operations usable with theoperation set forth in the flow chart of FIG. 4.

FIG. 6 is a simplified signal flow diagram of a start and cycle portionof the FIG. 2 illustrated apparatus.

FIG. 7 is a simplified signal flow diagram of a write resynchronizationcircuit usable with the FIG. 2 illustrated apparatus.

FIG. 8 is a simplified signal flow diagram of a read resynchronizationand terminate circuit usable with the FIG. 2 illustrated apparatus.

FIGS. 9 and 10 are diagrammatic representations of deskewing withread-back signal information contents and selected control signalsduring a resyncing operation of a dead track, respectively, for trailingor lagging and leading dead tracks.

FIG. it illustrates a resync signal having a pattern of 1s and 0s in arun-length limited recording code.

FIG. 12 is a simplified diagram of an ROC rotation controlled datalocation feature of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now moreparticularly to the drawings, like numerals indicate like parts andstructural features in the various diagrams. It is to be understood thatthe illustrations of signal flow diagrams and the operation flow chartsare to be interpreted as including functional representations ofmicroprograms in a general purpose programmable machine usable toaccomplish the functions and operations described herein. Sinceprogrammable machines can take various forms and are well known and theprogramming of same to accomplish the described functions can be varied,no detailed description of a particular program is included. Aprogrammer of ordinary skill can construct a program for practicing thepresent invention based upon the operation flow charts.

RECORDING SCHEMES It is well known that there are many types of systemsfor recording digital data, particularly on magnetic media. The presentinvention may be practiced with any form of recording on any media.While techniques of recording in various recording systems may varysomewhat in accordance with the characteristics thereof, theimplementation of this invention may be varied to accommodate suchvariations. For example, synchronization signals usable with variousrecording systems may vary somewhat in accord- Phase encoded recordingsusually utilize synchronization signals consisting of bursts of recorded0's. Padding within a data block to make the length of the data block apredetermined number of signals or digit positions consists of a stringor burst of recorded ls. Phase encoding is well known, and the signalrepresentation of 0s and 1's is likewise known. On the other hand,variations of such phase encoding may utilize bursts of 1s forsynchronization signals and bursts of 0s for padding in a data block.

US. Pat. No. 3,217,183, issued to L. H. Thompson et al., describes avariation of phase encoded recording. Another reference of interest isan article by R. C. Franchini on page 112 of the IBM TechnicalDisclosure Bulletin, July 1967.

In most magnetic-recording systems, the recording of data occurs only inone direction of tape motion. In accordance therewith, there is abeginning or end to each data block. Synchronization signals disposed atthe beginning and end of the block, respectively, are termed thepreamble and postamble. However, in many magneticmedia systems, readingcan occur in both directions.

Another recording scheme is NRZI in which a flux transition on therecord represents a binary 1 and no flux transition a binary 0. In NRZIrecording, the record is divided into cells each capable of. recordingone bit of binary data. Synchronization signals in NRZI recording are aburst of ls. For self-clocking purposes, an additionalclock-synchronizing signal may be periodically recorded among the datasignals.

The recording schemes described above, as well as other recordingschemes not described herein, can be modified by limiting the sequence(nm) of recorded signals to predetermine maximum lengths of ls or Us orboth. In such systems, the data to be recorded is converted into astorage code usually containing a greater number of signals than isusually used to represent a byte of data. For example. seven hits ofdata received by a recording system can be converted into a set of eightsignals. The characteristics of the eight signals are predetermined suchas to limit the bandwidth of the recording signals, (i.e., the maximumnumber of 1s or 0s in a string). It also may require that fluxtransitions of a certain character occur at least once in a small numberof cells. The usage of such predetermined fiux transitions will bedescribed later. It is known that the conversion of data representableby such run-length limited codes enhances the recording and readback inmagnetic-media systems. The utilization of storage codes assubstitutions for dataprocessing codes can be successfully used inpracticing the present invention.

As used herein, the words write" and record" are interchangeably used todesignate recording signals on a storage media. Similarly, the wordsread, read back, and sense are interchangeably used to designaterecovery of recorded signals from a storage media and conversion toappropriate digital signals.

RECORD FORMAT FIG. 1 diagrammatically illustrates one track of amultitrack block of data recorded in accordance with the teachings ofthe present invention. It is understood that any suitable recordingscheme may be utilized in this format. For purposes of discussion only,it is assumed that phase-encoded recording, described in U.S. Pat. No.3,217,183, is used with synchronization bursts of ls with padding burstsof 0s. The forward direction of tape movement is assumed to be fromright to left. Therefore, the beginning of the block of data is at thelefthand edge of FIG. 1.

The recorded block of data signals in each track includes preamble 10consisting of a synchronizing burst of signals B. The block is concludedby a similar set of synchronizing signals B in postamble 24.Intermediate the preamble and postamble are interleaved sets of datasignals D, marking signals M, and resynchronization signals B. Datasignals are grouped in sets 12, 16, and 22. The interleavedresynchronization signals B are grouped in resynchronization sets 14 and20. These latter signals enable resynchronization of a dead track withina block of data signals. It is understood that the number of sets ofdata signals and the interleaved resynchronization signals is a matterof design choice. Identifying the boundaries between the preamble,postamble, data signals, and the interleaved resynchronization signalsare a plurality of marker signals 11, 13, 15, 17, 21, and 23. Therecording of the illustrated block of signals begins from the left andproceeds toward the right in accordance with known techniques. The burstof signals are simultaneously recorded in all tracks. Defining one byteas being one cell in each track across a magnetic tape, a burst signalis all 1s in a byte. Marker signals are similarly constructed of all lsand all 0s in a plurality of bytes. The ensuing discussion for the mostpart is directed at a single track in a multitrack record.

It is desired, as will become apparent, that the number of bits recordedon the tape or other media between the beginnings of successivelyoccurring sets of data signals be the same or have the same remainderwhen divided by the number of ROC states. It is preferred all suchspacings be identical except the last spacing in a block which may betruncated. That is, the number of bits between the trailing edge ofmarker signals 11, 15, and 21 should be identical or have the sameremainder when divided by the number of ROC states. This spacing isrepresented by double-ended arrows 26. The length of the set of datasignals 22 is not important msofar as reading from left to right isconcerned. However, in systems where reading occurs in both directionsof tape motion, the length of data set 22 is important for maintainingthe relationship between postamble 24 and marker signal 17 the same asthe relationship between marker signals 13 and 17. As will becomeapparent, such consistency in spacing reduces costs in read circuits. Atthe end of a data block, it is quite difficult, it not imall) possible,to always ensure that the number of data signals 22a within set 22 willfill all the predetermined number of digit positions (for example,1,024). To make the remainder when data set 22 is divided by the numberof ROC states the same as the other data sets 12 and 16, a subset 22b ofpadding signals P are added. Such signals P are either a strong of Us ora string of 1s in accordance with the definition of the recordingsystem. For convenience, marker signal 23 is disposed between subset 22aof data signals and padding signals in subset 22b.

The illustrated format of tape recording enables resynchronization of adead track as well as the requeuing of a reactivated track in amultitrack system within the block of data signals. Later, a moredetailed format and circuit timing relation is defined in Table I. It isnot necessary to continue dead-tracking throughout the block of datasignals, thereby permitting a longer block of signals to be reliablyrecorded and reproduced than heretofore was generally practiced.

Preamble 10, postamble 24, and synchronizing signals B are strings of isSimilarly, the interleaved resynchronization signals B are strings of1s. For simplicity, all bursts of signals B should have the same lengthand characteristics. The end of preamble 10 is indicated by markersignal 11. All marker signals used in the first-described embodimenthave two bytes respectively having all ()s and ls recorded therein atthe beginnig of a set of data signals and all ls and Os recorded thereinat the end of a set of data signals. Therefore, the beginning of theblock of data consists of a string of ls in preamble 10 and a 0 and a 1in marker signal 11.

Data signals D are any mix of l and Us or may be permutation codes. Eachset of data signals may be of any predetermined length. In oneconstructed embodiment of the present invention, each set of datasignals was arbitrarily selected as containing a maximum of 1,024 cellsor digit positions per track, or l,024 bytes of data in a multitrackrecord. The last set of data signals 22b may contain fewer than 1,024 aswill become apparent.

Reproducing the recorded data signals D, shown in FIG. 1, may beaccomplished by reading in either direction. In reading from left toright, preamble 10 is first read to synchronize the self-clockingread-back circuits. Upon detection of marker signal 11, the read-backcircuit establishes a predetermined count (1,024) for counting datasignals from set 12. Data signals 12 are then read. Upon detection ofmarker signal 13 and the completion of the predetermined count, theread-back circuit discontinues sending data signals and prepares to readset 14 resynchronization signals B.

Such a read operation (reading a set of data signals and a set ofresynchronization signals) is repeated until either the detection ofpostamble 24 or receipt of a stop read signal from control circuitry(not shown). If the illustrated track had been deadtracked (i.e., thesignal envelope of the read-back signal fell below an amplitudethreshold or a phase error was detected), the read-back circuitrynormally would automatically ignore any signals received from suchtrack. By use of error correction codes, the dead-tracking can becompensated for in some instances in a control unit, which is not thesubject of the present invention. However, in reading back the formatillustrated in FIG. 1, the sets of resynchronizing signals are utilizedto resynchronize the channel clock within the block of signals. Ifresynchronization is successful, the next-occurring set of data signalsis read. Therefore, the dead-tracking function can be aborted within theblock of data by an interleaved set of resynchronizing signals B. Upondetection of a marker signal, the readback circuit is activated to readthe next-occurring set of data signals.

Also, in magnetic tape recording, it is desirable to have expansionspace in a block of data. Padding signal 22b can provide such expansionwithout subsequently altering the length of a data block. It is alsounderstood that such padding signals may be inserted in any of the setsof recorded data signals for permitting growth of the record anywherewithin the data block.

In the FIG. 1 illustration, marker signal 23 being all ls across thetape followed by all Os across the tape, is efiectively extended by thepadding 0 signals. The last padding 0 abuts the first 1 signal inpostamble 24. There is no need for a marker signal at this point becausethe 0-] change signifies the beginning of postamble 24.

Reading in the reverse direction is Substantially identical to theforward direction. Marker signals 23, 17, and 13, respectively, signifythe ends of sets of recorded data signals. A ditference arises in thatfor deskewing, the later-described read-in counters (RIC) for thevarious record tracks are initiated at the 1-0 change between postamble24 and padding signals P. This establishes a fixed relationship betweenthe state of the ROC and marker signal 21. Such action is more fullydescribed later. If the counters are always in the same signal stateupon the reading of such marker signals, the first occurring L datasignal (i.e., the first cell being scanned) may always be loaded intothe same relative position in the deskewing apparatus. his simplifiesdeskewing and the control functions related thereto. It also facilitatesrequeuing a dead track in accordance with teachings of the presentinvention. The reasons for such simplification need not be delved intofor purposes of understanding the present invention.

GENERAL DESCRIPTION FIG. 2 is a simplified illustration of amagnetic-tape subsystem using the teachings of the present invention andconnected through communications channel 30 to utilization means, suchas a central processing unit (not shown). The subsystem, as usual, has aplurality of tape handlers 31; only one of which is activated forreading or writing at a given time. Tape control system 32 selectivelycouples one of the tape handlers 31 to channel 30 such that data can berecorded on or read from a magnetic tape (not shown) being processed.The invention is illustrated by certain portions of such tape control;those certain portions being accented. It is understood that many othercontrol circuits are necessary to the successful operation of amagnetic-tape subsystem; such other control circuits arediagrammatically illustrated by box 33 labeled OTHER TAPE CONTROLS(OTC). Such OTHER TAPE CONTROLS (OTC 33) include motion controls. ON andOFF controls for the respective tape handlers, and the like. Signals foreffecting such other control functions are exchanged between OTC 33,channel 30, and tape units 31 over cables 34 and 35.

Some control signals intimately associated with the practice of thepresent invention are now described. First, two control signals suppliedfrom channel 30 are described. A COMMAND OUT (CMD OUT) signal issupplied over line 36 from channel 30 to tape control 32. CMD OUTinitially sets up OTC 33 in a read or write operation. Signals termedcommand are sent to OTC 33 along with CMD OUT for conditioning OTC 33 toperform certain functions. CMD OUT sent during performance of a givenfunction indicates to tape control 32 that no more tape functions aredesired. In a read operation, such a CMD OUT is interpreted as do notsend any more data to channel 30 from the activated tape handler 31. Ina record or write operation, such a CMD OUT indicates there is no moredata to be recorded. The latter two instances of CMD OUT are the onlyones referred to herein.

A SERVICE OUT (SVC OUT) signal, supplied over line 37 to OTC 33 during aread operation, indicates that channel 30 has successfully received onebyte of data supplied from a tape handler 31. During a write operation,SVC OUT is interpreted as indicating that data to be recorded is nowavailable from channel 30.

Control signals are also supplied from tape control 32 to channel 30.Many of these are indicated by cable 35.

A control signal of interest to the practice of the present invention isthe CHANNEL SERVICE IN (CHL SVC IN) signal supplied over line 38a. Thislatter signal is initiated by OTC 33 and supplied throughstart-and-cycle circuit 52 for reasons that will become apparent. In aread operation, CHL SVC IN signal indicates that one byte of data hasbeen read from a tape in tape handler 31 and is available to channel 30.During a write operation, CHL SVC IN is a request for channel 30 tosupply the next byte of data to be recorded. Upon supplying same,channel 30 supplies a SVC OUT control signal indicating that such byteof data is available or CMD OUT for stopping the write operation.

These just-described signals are shown as being received through OTC 33.While those control circuits are not described in detail, the ensuingdetailed description of tape control 32 and known tape control circuitswill make the means effecting such exchange apparent.

Data flow between an activated tape handler 31 and channel 30 is via thebuffer registers 40. Buffer registers 40 include deskewing apparatus 49,as later described. In a read operation, data sense-and-detect circuits41 (one circuit for each record track) receive signals from one of therespective tape handlers 31 and supply digital data signals to butterregisters 40. Such signals, while not yet deskewed, are in digital form.Data sense-and-detect circuits 41 include self-clocking circuitrynecessary for the successful readback of high density magnetic records.Also included are amplitude and phase threshold circuits for detectingwhether or not recorded data signals are being successfully recoveredfrom the tape being processed. Such circuits are well known and will notbe further described for that reason.

Data flow during a write operation is from channel 30, through thebuffer registers 40, thence to write circuits 42 (one circuit for eachrecord track). Write circuits 42 convert the received digital signalsinto the appropriate recording waveforms in accordance with the selectedrecording scheme and supply same to the activated tape handler 31 forrecording on tape. Write circuits 42 may include a set of finalamplifiers with the actual recording signals being distributed directlyto the recording transducers of any tape handler 31 over a Write bus.

Data signals to be written on a tape in a handler 31 are supplied to I/Oregister 48 in buffer registers 40. Suitable gating control circuits(not shown) gate the signals directly to write circuits 42 for arecordation on a magnetic tape. The one exception to this statement isdescribed in detail later. All of the other registers shown withinbuffer registers 40 are used in the read-back operation. The digitalsignals being processed during a read operation are first supplied todeskewing apparatus 49. Such deskewing apparatus is well known in theart. For example, a deskewing system using a read-in counter (RIC) 43for each track and a single readout counter (ROC) 44 is described byFloros in US. Pat. No. 2,921,296. RlCs 43 keep track of the digitalsignals as they are received from data sense-and-detect circuit 41. Whenall RICs 43 have proceeded from a predetermined signal condition, onebyte of data has been aligned and is ready to be transmitted to channel30. At this time, ROC 44 is altered by one count and, simultaneouslytherewith, one byte of data is transferred to error register 45. Inerror register 45, error detection and correction functions areperforned. Such functions are not a part of the present invention and,therefore, will not be further described. From error register 45, thebyte of data is transferred to read I register 46, thence to read 2register 47 and read 3 register 55. The number of these registers is adesign choice made with respect to timing. From read 3 register 55, thebyte of data is supplied to I/O register 48. If the read-back circuitryof FIG. 2 is currently reading back data signal D, a CHL SVC IN signalis supplied to channel 30 to indicate that I/O register 48 has one byteof data available for transfer to channel 30. When readingresynchronization signals B, the CHL SVC IN signal is never sent tochannel 30, hence resynchronization signals are obliterated as newsignals are received.

The description of FIG. 2 up to now has concerned itself with prior tapecontrol devices. The additional circuits used to implement the presentinvention in the FIG. 2 illustrated control include read resync circuits50, write resync circuits 51, and an illustrative modification of thesequence control of OTC 33 is set forth in start-and-cycle circuits 52.It is to be understood that some of the individual functions performedand circuits illustrated in these latter three circuit configurationsmay have been found in prior tape control units. However, the functionsperformed by these three circuits and the interconnections therebetweenand with the other portions of the tape subsystem as set forth in thelater-described fiow charts illustrate how the invention can bepracticed. An understanding of the detailed connection illustrated inFIG. 2 will become apparent from the descriptions of the three circuits.Generally, OTC 33 and start-and-cycle circuits 52 initialize the controlunit and respond to the recorded signals for detecting theresynchronization bursts, for inhibiting transfer of suchresynchronization signals to channel 30, and respond to a CMD OUT signalfor stopping operations. Read resync circuits 50 controlresynchronization of a dead track and requeue such dead track into thedeskewing operation performed by deskew apparatus 49. In this conection,read resync circuits 50 have a close interaction with the deskewingoperation and data senseand-detect circuits 41. Write resync circuits 51program the operation of the tape system such that resynchronizationsignals are properly written between sets of data signals beingrecorded.

FORMAT-TO-SYSTEM RELATIONSHIPS Before proceeding into the description,the format relationship of data signals on the most lagging track on thetape with the readout counter (ROC), the burst counter, and the bytecount is described with respect to Table I. The RIC of the most laggingtrack determines the ROC count; therefore, the one most lagging trackonly is considered. In the Table, D indicates data signals and may beeither a zero or a one, C indicates a check digit, M indicates a markersignal which may be either all zeros or ones in accordance with theprevious discussion. The relationhip of s and ls for the illustratedembodiment is shown in parenthesis under the MM designations. Numbersare counts in the respective counters.

The burst counter, used during write operations, to record or write aresync burst is shown in FIG. 7. When the burst count is equal to l, acheck digit (CRC) is transferred for recording; when equal to 2 and 3,the marker signal is written (i.e., all ls then all US). In steps 4through 31, 28 all 1 bytes" are written. In burst count steps 32 and 33,the marker signal consisting of all Os then all ls is written. In step34, writing of data is reinitiated. The byte count is shown as adecrementing count. The last data byte is B=0, which corresponds to ROCin the forward direction of equal 14. At the right-hand edge of Table I,the byte counter is shown as being set to 1,024 at the first data byteand decremented to 1,023 at the second data byte.

In observing Table I, it should be remembered that the data byte alignedwith ROC forward=l4 does not reach I/O register 48 until several cyclesof ROC. That is, ROC 44 counts the data bytes as they are transferredfrom SKB 49 to read 1 register 46. That data byte will not reach the I/Oregister until ROC=3. Check digit does not reach I/O register 48 untilROC forward=4. Therefore the SVC IN signal to channel 30 is notforwarded from control unit 32 until after ROC 44 has reached a count ofat least 5. Then SVC OUT is received from channel 30. This is animportant point to remember in considering the timing of the resyncbursts and the read resync cycle illustrated hardware embodiment.

RECORDING Recording signals on a magnetic tape using the presentinvention are first described. Generally, there are two approaches torecording in accordance with the present invention. The first approachis to write a number of data signals D within a block of data signalswithout knowing beforehand the total number of data signals to berecorded. The first approach is described in detail with respect toFIGS. 3 and 7. The second approach is to write a predetermined number ofdata signals to form a block of such data signals having interleavedresynchronization signals. The second approach is described generallylater as a modification to the first approach. Because all recordingscan be efi'ected without knowing beforehand the number of signals to berecorded, the first-mentioned approach is described in detail. Forpurposes of discussion, in both approaches, it is assumed that one byteof data is recorded across the tape at a time. The byte of data mayconsist of eight binary digit positions plus parity. The parallel re-TABLE I Signals D C MG) Mtu) 1. .1 1 1 1 1. 1 him) MU] D D Burst counterl 2 3 4 16 17 18 19 31 32 33 34 ROC forward." 14 15 0 1 2 13 14 15 U 113 14 15 0 1 ROC backward t) 15 14 13 12 1 0 15 14 13 1 0 15 14 Bytecount 0 0 0 0 0 0 0 0 (l 0 0 0 0 1,024 1,023

The write and read-back systems are designed such that ROC will pass areference count at predetermined points of the recording within the datablock. It is to be appreciated that ROC changes from 15 to 0 severaltimes while reading data. However, upon the onset of a set of datasignals, ROC should be moving from 15 to O in either direction ofreading. As shown above in the forward direction which corresponds toreading Table I from left to right, ROC changes from 15 to 0 upondetection of the marker signal at the trailing end of the all ls resyncburst. The resync burst contains 28 ones such that the marker signalsplus the resync burst corresponds to two rotations of ROC. At theright-hand edge of Table I, it is seen that ROC in the forward directionchanges from 15 to 0 when reading the trailing end marker signal, asdesired. In the backward direction, the marker signal ROC countrelationship is somewhat dilferent because of the check digit in thedata subset. Leaving the resync burst, which is now the left-hand sideof Table I, ROC=15 at the check digit and goes to 0 for thefirst-encountered data byte.

cording of such a byte requires one cell in each of nine data tracks.

To record an unknown number of data signals and ensure there is dataavailable to be recorded, it is desirable for the tape system to firstobtain one byte of data to be recorded from channel 30 before the tapemotion in a handler 31 is initiated. Therefore, in preparing forrecording, control 32 requests the first byte of data before initiatingmotion of the tape. Referring to FIG. 3, the first step in theprogram/hardware sequence flow chart is to make available one byte ofdata to be written. As soon as one byte of data is available, a motioncontrol signal is issued by OTC 33 over cable 34. When the tape hasreached operating velocity, an indicating signal is supplied over cable34 to OTC 33. Preamble 10 is then written by repeating steps 61 and 62.In step 61, write initial sync burst signal (one signal B in a burst ofsuch signals B) is written in each track on the tape. In step 62, thenumber of signals B actually written in each track is compared with thenumber desired to be written in preamble 10.

1f the count is not complete, operation is returned to the input of step61. When preamble count is complete, operation proceeds to step 63 towrite one marker signal.

The marker signal in the illustrated embodiment consists of writing allOs across the tape, followed by writing all is across the tape. Any formof marker signal, of course, can be used. Next, in step 64, the byte ofdata made available in step is transferred to write circuits 42.According to step 65, as the byte is transferred, a later-described bytecounter in start-and-cycle circuits 52 is activated to tally the numberof recorded bytes. This tally is used to determine the size of sets ofdata signals.

Then, in step 66, the write data cycle in start-and-cycle circuits 52 isinitiated. At this time, the CHL SVC IN signal is forwarded to channel30 enabling another byte of data to be transferred to I/O register 48.In this discussion, it is assumed that the transfer rate of channel 30is much higher than the recording rate in tape handler 31. Therefore,the data signals to be recorded are available in l/O register 48substantially simultaneously with the transmittal of the CHL SVC INsignal.

The writing of one set of data signals is completed by the next loop ofsteps 67 through 71, inclusive. If 1,024 digit positions occur in eachtrack, then 1,023 bytes of data are recorded by such loop cycling itself1,023 times. Remember, one byte has already been recorded. In step 67,one byte is transferred from I/O register 48 to write circuit 42 forrecording. In decision step 68, the receipt or nonreceipt of a CMD OUTsignal is sensed.

If the CMD OUT signal has been received, further writing is stopped anda write termination operation, later described, is initiated. If no CMDOUT signal has been received, the write operation proceeds to decisionstep 69. In step 69, a test for receipt of the SVC OUT signal is made.If it has not been received, no data is available H from channel 30.Steps 68 and 69 are repeated until SVC OUT is received. Normally, thewait for a SVC OUT signal is short. As soon as SVC OUT is received, instep 70 the byte counter in start-and-cycle circuit 52 is altered byunity. Then, in decision step 71, the byte counter is sensed to seewhether or not the byte count is complete (i.e., whether or not 1,024bytes have been recorded). If the count is not complete, the sequence isrepeated. If it is completed, then during step 73 the last byte of datais transferred to write circuit 42. This means that, in decision step71, a byte count of 1,022 is tested with the last byte being Writtenduring step 73, making a total of 1,024 bytes. In many recordingsystems, it is desired that a longitudinal (track) or cyclic redundancycheck di it (CRC) be recorded. This recording occurs during step 74.This check digit may be one byte across the tape between the last datasignal and the marker signal 13, for example.

The write operation in steps 75-82 then writes marker signal 13 and set14 of resynchronization signals B. Before initiating the writing of thefirst resynchronization signal, in step 75 the receipt of CMD OUT isagain tested. If CMD OUT has been received, a write terminationoperation is initiated. If a CMD OUT signal has not been received, thenthe receipt of a SVC OUT signal is sensed during step 76. It isremembered that before data is initiated to be written, it is desired tohave one byte of data in register 48. This is the purpose of testing forthe receipt of a SVC OUT and not initiating further operation until SVCOUT has been received. As soon as SVC OUT has been received, during step77 a marker signal, such as marker signal 13 (all 1's then all Os), iswritten. Immediately after writing the marker signal, STOP is sensedduring step 78. If STOP is on, then postamble 24 is written, as will belater described. If STOP is off, resync burst 14 is written in steps 80through 82. In step 80, one signal B is written in one cell position ofeach track. Then, during step 81, STOP is again sensed. If STOP is off,which would be the case in writing a resync burst, in step 82 the tallyof the recorded signals B is sensed. If it is desired to write 24signals in a burst, then the loop 80, 81, and 82 is repeated until thetally has reached 24. At that time write operations return to step 63(FIG. 3A), which writes marker signal 15. Then, the above-describedcycle for writing a set of data signals is repeated. The above-describedoperations of alternately writing data signals and burst ofresynchronization signals are repeated until CMD OUT is received, atwhich time the writing operation is terminated. Termination includesrecording padding signals P in data set 22 and Writing postamble 24.

Because of the nonpredetermined length of data to be recorded, a CMD OUTsignal for terminating the write operations can be received at any time.For this reason, CMD OUT is sensed in steps 68 and 75. In step 68, theCMD OUT is sensed while Writing a set of data signals. If a CMD OUT hasbeen received, the Write operation is terminated. First, a check digitmust be written. To set up the appropriate sequences, in step 86 alater-described resync burst counter is set to 1. This action enables asequence to write a check digit in step 74. Since CMD OUT has alreadybeen set, the operation branches to step 87 which sets a stop latch instart-and-cycle circuit 52. This action indicates that STOP is on.Marker signal 23 (all ls, then all Us) is written during step 77. Instep 78, since STOP is on. deceision step 88 determines whether or notthe byte count has been complete (i.e., whether the correct number ofpositions have been used to complete data set 22). Such correct numberis any number which is an integral multiple of the ROC modulus. 1n thepresent illustration, such correct number is an integral multiple of 16,the number of ROC 44 stable states. If the byte count does not bear thecorrect relationship to the number of ROC states, the byte count isaltered by unit in step 89 and then step 78 is repeated. This smallsequence loop is repeated to complete the byte count. This action writesall 0 padding bytes.

The operation proceeds to step 80 in which one postamble signal B iswritten. Since padding signals are (is and burst signals B are ls, theend of the block is indicated by the 0 to 1 transition. With no 0padding signals, the all Os byte of marker signal 23 is the last all 0signal in the data block. Then, in decision step 81, STOP being on, theoperation goes to END ls (postamble) count decision step 90. Thepostamble count is preset in step 86 such that a set number of bursts ofsignals B are written in repeated steps 80. The number of postamble allls bytes may be designed into the later-described hardware or beprogrammed. The postamble count is altered (incremented) in step 92 ineach repetition. Upon the completion of the postamble count, the flowchart is exited at line 91 to terminate the write operation in a knownmanner.

READING The sequence of operations for reading recorded data in theformat shown in FIG. I is now described. It is assumed that the tape ismoving and the read circuits have been initialized; that is, the readcircuits are all activated to the proper condition and awaiting thedetection of a block of data. Upon the detection of readback signalenvelopes by data sense-and-detect circuits 41, the read operation isinitiated in step of FIG. 4. Step 100 is not completed until preamble 10or postamble 24 has been read. This completion is detected by sensing anall Os byte in marker signal 11 after reading the burst of all ls bytes.The first decision is performed in step 101, wherein the direction ofread is determined. If the read is in a forward direction, paddingsignals 22b need not be eliminated from the read-back; therefore, theread operation goes immediately to decision step 102 which detects whenROC 44 has a state equal to 5. This state corresponds to the first byteof readback data having progressed through bufi'er registers 40 into I/Oregister 48. The number 5 is derived from timing con- 13 siderations.Other hardware designs would alter the state of ROC 44 at which the readsequence is initiated. In any event, when the ROC 44 has reached apredetermined state, a read sequence is initiated, indicated by line103.

However, if the reading operation is in the backward direction, decisionstep 104 is first performed. This step detects marker signal 23. If nomarker signal has been detected, padding signals 22b are being read.During this cycling, the byte count is altered in step 109 and there isno transfer of signals to channel 30. The read-back padding signals aretransferred into read-1 and read-2 registers 46 and 47 for the detectionof marker signal 23. After the detection of marker signal 23 in step105, a check digit is transferred to error detection circuitry (notshown). It will be remembered that the last item Written in any set ofdata is a check digit. Therefore, when reading in the backwarddirection, the first data to be encountered is this check digit. Step106 is a two-cycle delay such that the first byte of data signals D,following the H marker signal in registers 46 and 47, is transferredinto I/O register 48. Upon the completion of delay in step 106, the readsequence is initiated, indicated by line 103.

Detection of marker signal 23 may also be accomplished within datasense-and-detect circuits 41. This approach is followed in thelater-described hardware embodiment. Generally during a backward readoperation, detection of a first occurring 1 signal after detection of asignal indicates marker signal 23. The leading track then establishesdetection of marker signal 23.

The first step 107 in read operation sets a steering latch instart-and-cycle circuit 52. This latch being set signifies the beginningof a read operation and enables circuit 52 to cycle until one set ofdata signals is read. In step 108, one byte of data is read. This meansthat one byte of data is transferred from deskewing apparatus 49 to theerror detection and correction register 45 under the control of ROC 44.During the same step, the byte counter in start-and-cycle circuit 52 isaltered by unity. When reading set 22 of data signals, the byte countincludes padding signals P.

During decision step 110, the status of the byte counter is sensed. Ifthe byte count is complete, and of a data set is indicated; reading datais terminated, and a read resync cycle 111 is initiated. Read resynccycle 111 is described later with respect to FIG. 5. This cycle enablesthe automatic resyncing of a dead track and inhibits the transfer ofresynchronization signals B through I/O register 48. It is also used toterminate a read operation. If the byte count is not complete, decisionstep 112 is initiated. If a marker signal is detected, end of data isindicated and the read resync cycle of FIG. is initiated. Only if nomarker signal has been detected and the byte count is not complete isstep 103 reinitiated and repeated until one of the two end of dataconditions is met.

The initiation of the read resync cycle of FIG. 5 includes resettingsteering circuit in step 116. The direction of tape motion is againdetected in decision step 117. If tape motion is in the forwarddirection (i.e., from left to right in FIG. 1), a check digit (CRC) istransferred to an error detection and correction circuit in step 118. Ifthe reading is in the backward direction, the check digit has alreadybeen transferred, and the operation proceeds directly to decision step119. This decision step determines the state of ROC 44. Before aresynchronization burst can be read, all data must have been transferredfrom I/O register 48 to channel 30. In the illustrated hardware design,the last data byte resides in I/O register 48 when ROC: l2. Returningnow to the forward direction reading, after the transfer of the checkdigit, the condition of ROC 44 is checked in decision step 120. In theparticular embodiment, when ROC=4, everything is appropriate forentering step 119. If, however, ROC 44 contains any number but 4, theread operation is stopped. In the illustrated embodiment, the checkdigit should be transferred when ROC 44:4. If operation is ditferent,either the data set being read is the last data set in the block andcontains less than 1,024 bytes, or a fautly read operation has occurredand should be stopped. Control circuits in OTC 33 determine which is thecase by measuring the length of the remaining data signals and settingan error latch (not shown) if the termination was premature.

Upon detection of ROC 44:12, the read resync operation is initiated bysetting a phase or resynchronization test for dead track in step 121.This setup enables testing whether or not the dead track has beenresynchronized at that point in the resynchronization burst. In decisionstep 122, deskewing apparatus 49 has been stepped to reference stateROC=15. In the illustrated deskewing apparatus there are 16 deskewingpositions corresponding to ROC=0 through ROC=15. Change from ROC=15 toROC=0 is arbitatrily defined as a reference change. For requeuing a deadtrack into deskewing apparatus (SKB) 49, the apparatus should be in awell defined operational state. Control 32 is cycled until thiscondition occurs. In step 123, the requeuing of the dead track intodeskewing apparatus 49 is set up. This action activates circuitry orprogramming for detecting the successful readout of a present dead trackinto deskewing apparatus 49. In step 124, ROC 44 is cycled until itreaches state 14. This signal state corresponds to a predeterminednumber of resync bytes of all ls being transferred through deskewingapparatus 49. During the delay, the dead track is hopefullyresynchronized and made ready to be reactivated. The number of resyncsignals processed corresponds to the length (16 bytes) of deskewingapparatus 49.

The next step in the flow chart is to test the success of theresynchronization of the dead track. In step 125, a test circuit isactivated. In decision steps 126 through 128, the test is repeatedthroughout the resync burst being read. In step 126, a test is made ofwhether or not at least three tracks are not supplying satisfactorysignals. In case three tracks are not supplying satisfactory signals thereading operation is aborted. Such a condition indicates either end of adata block or readback is entirely unsatisfactory. If, however, lessthan three tracks are supplying no signals, decision step 127 isinitiated. The test is whether any RIC 43 has a value of 13. Thismagnitude corresponds to the detection of the maximum skew in theillustrated read-back system. If none of the RICs have a value of 13 indecision step 128, there is a test made of whether or not an ROC step to0 has been initiated. If no ROC step to 0 has been initiated, steps 126,127, and 128 are repeated. ROC 44 stepping from 15 to 0 indicatessuccessful readback from the previously dead track. That is, one byte ofsignals has been assembled into SKB 49. The occurrence of any RICequaling 13 is an indication that the dead track has not providedsignals to deskewing apparatus 49 (i.e., maximum skew has beenexceeded). This relationship is described later with respect to Table Iand FIGS. 9 and 10. Therefore in step 129, dead-tracking of such deadtrack is reinitiated. If an ROC step to 0 has been initiated in decisionstep 128, a successful resynchronization of the previously dead trackhas occurred. Of course, it must be remembered that, if there are nodead tracks, step 128 is performed immediately. This completes theread-back of a resynchronization burst.

Next, the read-back circuitry is conditioned by reenter read sequence130 for reading the next set of data signals. In decision step 131, thedirection of tape motion is again detected. If the motion is in theforward direction, decision step 102a, which corresponds to decisionstep 102 of FIG. 4, is performed. If it is in the backward direction,steps 132 through 134 are performed. In decision step 132, the conditionof ROC 44 being equal to 4 is sensed. In step 133, a check digit istransferred to the correction circuitry in the same manner as in step ofFIG. 4. In decision step 134, there is a waiting period until RO C 44:6.Normally, it will be equal to 6 since the transfer of check digit instep 133 takes one cycle and advancing the first data byte to the I/Oregister will take one cycle. Upon completion of steps 102a or 134, theread sequence is reinitiated by performance of step 107 in FIG. 4. Theabove-described sequences are repeated until the detection of the end ofthe block of data. This may be accomplished in decision step 126 (FIG.wherein more than three tracks do not supply a read-back signal.

The abovedescribed flow charts of operations can be implemented byprogramming, hardware sequences, or a combination of both. A simplifiedillustration of a hardware implementation of the flow charts isdescribed. The description of the hardware will be keyed to theflowcharting for a clearer understanding of the illustrated embodiments.

WRITE HARDWARE Write operation hardware is described with particularreference to FIGS. 2, 6 and 7. The description assumes that the usualcontrol signals have been transferred through channel 30 to OTC 33 forinitiating a write operation. OTC 33 is supplying a continuous controlsignal on line 135 indicating a write operation is being performed aswell as supplying a periodic write clock signal (pulse) on line 136. Ina practical embodiment, the write clock pulse is derived from a singlesource and within OTC 33 divided into a plurality of separately timedpulses. This approach is one of known design choice used to avoid pulseoverlapping problems, other critical electrical signal-timing problems,as well as reducing the number of circuits in control unit 32. Forpurposes of understand the present invention, it is unnecessary to delveinto such engineering design niceties. Further, for simplicity, theactual connections are not shown but are understood to be made be tweenthe various figures. In FIG. 6, preamble control 137 is first activatedby OTC 33 to write-preamble of FIG. 1. This corresponds to performanceof steps 61 and 62. Action is initiated by the write clock, the writesignal, SVC OUT signal indicating that one byte of data is available, asin step 60, and start pulse on line 138. Preamble 10 is written aspreamble control 137 supplies a write-allls signal over line 148 towrite resync control 51. Control 51, in turn, supplies a write-all-lssignal over line 149 to write circuit 42. Upon completing writing thepreamble, preamble control 137 writes marker signal 11, as set forth forstep 63. It is recalled that this consists of writing an all Os byteacross the tape and then writing an all ls byte. An Os signal issupplied over line 188 followed by a write-all-ls signal supplied overline 148 to write resync circuit 51. Circuit 51 transfers these signalsover lines 149 and 189 to write circuit 42. Since recording preambles ofall ls or all US followed by a marker signal is well known, the detailsof preamble control 137 are not described. The later-described burstcounter 163 of FIG. 7 could be used to writepreamble 10. Thispossibility will become apparent from the description of postamble 24recording. Such sequencing is readily established by microprogramming.

Immediately after the marker signal of all 0s and all ls having beenrecorded, the first byte of data to be recorded is sent to writecircuits 42 for recording. Before tape motion is initiated, OTC 33effected transfer of the first byte of data from channel 30 to I/Oregister 48. Details of such transfer are known and not pertinent to anunderstanding of the present invention. One manner of obtaining andtemporarily storing the first byte of data is the utilization of thestart pulse on line 138 to transfer the byte of data to byte-storageregister 160 (FIG. 6). This transfer is effected by AND-circuits 168which receive the data signals from I/O register 48. (This latterconnection is not illustrated in FIG. 2.) Therefore when a preamble isstarted by a start pulse, the first byte of data is made readilyavailable within the control unit by transferring it to the byte storageregister 160. Upon completing premable 10 by preamble control 137, an

16 end of preamble signal is supplied through OR-circuit 144 to actuateAND-circuits 147, thereby transferring the first data byte to writecircuits 42. It may be noted that the start pulse on line 138 is notsupplied until after the channel has supplied a SVC OUT signalindicating that the data byte is available.

The end of preamble signal also conditions the control unit to performsteps 64 through 71 of the write flow chart. This is accomplished byenabling AND-circuit 139 to pass a write clock pulse from line 136 toset steering latch 141. OR-circuit 140 will pass other signals duringthe write operations for setting steering latch 141 at the end of awrite resync as well as during read operations.

Steering latch 141 gates the next SVC IN on line 38 through AND-circuit142 to generate CHL SVC IN on line 38a. This signifies to channel 30that control unit 32 is ready to receive the second byte of data. Thefirst byte, of course, remains stored in byte storage register 160 untilpreamble 10 is written.

The tally of the number of data bytes that have been recorded is held inbyte counter 143. The contents of byte counter 143 are altered inaccordance with steps and 70. Since SVC IN indicates completion of onebyte being recorded, the line 38 SVC IN signal is gated throughAND-circuit 142 to byte counter 143. The AND-circuit 142 output is alsosupplied through OR-circuit 173 as the CHL SVC IN signal. AND-circuit142 is enabled to pass the SVC IN signal only when latch 141 is set(i.e., during recording of data in a write operation).

The SVC IN signal is generated by known circuits. When OTC 33 determineswrite circuits 42 have recorded a data byte, it generates a SET SERVICEIN (SET SVC IN) pulse. This pulse is supplied over line 190 to set SVCIN latch 191. Latch 191 then supplies the SVC IN DC signal until resetby either a SVC OUT signal, CMD OUT signal, or a later-described PSEUDOSVC OUT (P SVC OUT) signal.

Step 68 is performed in the write resync circuits of FIG. 7. During awrite operation, the CMD OUT signal sets WRITE STOP latch 151. CMD OUTtogether with the line WRITE signal enables AND-circuit to pass the nextoccurring SVC IN signal for setting WRITE STOP latch 151. Such usage ofSVC IN ensures that the meaning of the CMD OUT signal is stop. Remember,as described before, CMD OUT may have several meanings depending uponthe inbound signal at that moment. Stop is defined as CMD OUT in answerto SVC IN (i.e., CMD OUT is received after a function is being performedby control unit 32). Reset line 152 indicates that, during initialize,WRITE STOP latch 151 is reset to the inactive condition. When CMD OUTsignal is not received, no action is taken.

Then, TEST SVC OUT test step 69 is performed. SVC IN again samplessteering AND-circuit 142 (FIG. 6) to generate CHL SVC IN signal, whichalters byte counter 143 by unity and gates out one byte of data from l/Oregister 41 to write circuits 42. It also notifies channel 30 to supplyanother data byte for recording.

Completion of writing one set of data signals is determinated by 13:0detector 155 (FIG. 6) indicating that byte counter 143 contains zero (BO). If 13:0 is not supplied, the just-described write cycle is repeated.As later described, if 13:0, the write resync circuits of FIG. 7 areactivated to reset steering latch 141 for terminating the writeoperation (one set of data signals has been recorded). This action isaccomplished when SVC OUT is received over line 37 and B:0. AND-circuit157 is jointly responsive to these signals and a write signal on line135 to set END OF DATA latch 158. When set, latch 158 activates the FIG.7 write resync circuits by setting write resync latch 161. To resetlatch 158, AND-circuit 169 jointly responds to write signal on line 135and the SET SVC IN signal on line 190.

A resync burst, longitudinal check digit and the marker signals arewritten only after the first byte of data for the next data set to berecorded has been received. Such byte of data is indicated as beingavailable by SVC OUT. SVC OUT is not available during the writing of thecheck digit, marker signals, and resync signals B. Since no additionalSVC OUT is received, a PSEUDO SVC OUT (P SVC OUT) signal is generated tostep the later-described write resync recordings. When data signals arebeing recorded, the SET SVC IN and SVC OUT signals step operations.During resync recording, SVC IN is gated by AND-CIR- cuit 195 (FIG. 6)through delay 196 to generate P SVC OUT. AND-circuit 195 is enabledwhenever steering latch 141 is reset (data is not being recorded) tosimulate responses from channel 30.

The number of resync signals B that have been recorded plus recording tomarker signals is tallied in burst counter 163 (FIG. 7). Counter 163 isstepped once each time AND-circuit 162 passes SET SVC IN. Circuit 162 isenabled by write resync latch 161 being set and writing not beingterminated, as indicated by a signal on line 213. This signal isdescribed later with respect to stop write sequencing. Counter 163supplies its signal state indications to burst count decoder 164, whichtranslates all signal states of the counter into one of 35 signalconditions. When burst counter 163 contains unity, step 74 of FIG. 3 isperformed. An activating signal is supplied over line 167 (FIGS. 7 and2) to OTC 33 for gating a check digit over cable 197 to write circuits42. The generation of such check digits is well known and is not furtherdescribed for that reason. Steering latch 141 is now reset byAND-circuit 192 supplying a signal over line 166 to AND-circuit 159. Thewrite clock pulse on line 136 is passed by AND-circuit 159 to resetlatch 141. AND- circuit 192 only supplies this resetting signal whenstop write latch 151 is reset (i.e. not a stop sequence).

At this point, there is a deviation in operation steps between FIGS. 3and 7. In the FIG. 3 embodiment, step 74 is executed before receipt ofSVC OUT. In FIG. 7, SVC OUT is received before a check digit is sent towrite circuits 42. Either embodiment is satisfactory. FIG. 7 could bemodified to gate the check digit upon B without waitnig for SVC OUT.

The next step is to record marker signal 13. In FIG. 7, marker signal 13is written during the two steps to write the marker signal of all ls andall 0s and occurs as burst counter 163 steps through counts 2 and 3. Atcount 2, a write all ls signal is supplied by decoder 164 throughOR-circuit 170 to write circuits 42. When burst counter 163 has a countof 3, a write all Os signal is supplied through OR-circuit 171 to writecircuits 42. Write all Us or all ls indicates the appropriate signal issimultaneously recorded in all tracks. This action completes the writingof the marker signal as set forth in step 77 of FIG. 3.

In burst counter steps 4 through 31, a burst of ls is recorded.Accordingly, when decoder 164 senses that the tally is equal to 4 (K=4),write-all-ls latch 172 is set. It supplies a write-all-ls signal throughOR-circuit 170 to Write circuits 42. A 1 is written in each and everytrack during each cycle of the control unit as burst counter 163proceeds through its count. When counter 163 has reached 32,write-all-ls latch is reset, thereby removing the writeall-ls signal.Also, during burst counter steps 32 and 33, marker signal is recorded bythe all-Os and all-ls signals being supplied in that order to writecircuits 42. Write resync latch 161 is reset by decoder 164, K=34signal, thereby terminating the writing of the resynchronization burstof signals. To restart recording of data signals in data set 16, line175 signal (K=34) simultaneously enables AND-circuit 176 to pass a writeclock pulse to set steering latch 141 (FIG. 6), resets write resynclatch 161 and gates the first data byte in register 160 (FIG. 6) towrite circuits 42. The latter is accomplished by K=34 passing from line175 through OR-circuit 144 to enable AND-circuits 147 of FIG. 6. Writeresync latch 161 being reset terminates resync signal recording.Steering latch 141, upon being set, automatically sequences writing thenext set of data signals in the same manner as heretofore described.

The above-described operations for writing sets of alternate datasignals D and resynchronization bursts B are repeated until the lastbyte of data has been recorded. This is signified by channel 30supplying a CMD OUT signal. The CMD OUT signal sets write stop latch 151of FIG. 7 to initiate sequences for terminating the writing operation.The write signal on line and SVC in signal on line 38 jointly enableAND-circuit 150 to pass CMD OUT to set write stop latch 151. Referringnow to FIG. 1, it is seen that the last byte of data may occur at anytime during the recording of a set of data signals having a maximumlength of 1,024 bytes. Therefore, to ensure that the truncated block ofdata bears the previously described integral multiple relationship tothe number of ROC states, it may be necessary to write padding signals Pin subset 22b. A write termination operation is then initiated whichincludes writing postamble 24. If CMD OUT is received at the completionof recording a set of data signals, a marker signal and postamble 24,are written. Pad l detector 216 is connected to the lower order four bitpositions or stages of byte counter 143. Therefore, detector 216 detectsa byte count within the modulus of ROC 44 to ensure a recording lengthhaving an integral multiple number of signals of the ROC 44 modulus.

When CMD OUT is received in a middle of a data set, marker signal 23 isfirst written followed by a burst of 0 signals represented in FIG. 1 bythe padding signals P. In reading in the forward direction, markersignal 23, which is an all-ls byte followed by an all-Os byte, signifiesthe end of data. Reading in the reverse direction, the postamble (i.e..all-ls), followed by a 0 signal indicates that data set 22 is beingread. However, the all-Os bytes indicate no data is to be transferredout of the control unit. However, the byte counter 143 may be talliedsuch that the count is proper when marker signal 21 is to be read. Datais transferred upon the detection of marker signal 23. Therefore, thewrite STOP sequence must record an all-ls byte followed by a sufficientnumber of all-Os bytes to make the length of the data set bear theintegral multiple relation to the number of ROC states and then recordan all-ls postamble. The above discussion assumes that the check digitassociated with the subset 22a of that data signal has been written.

Returning now to FIGS. 6 and 7, the STOP signal from latch 151 issupplied over line 200 to delay write terminate circuit 201 (FIG. 7).Circuit 201 enables the termination of write operations to be delayeduntil after the padding signals and preamble 24 have been recorded. STOPis also supplied to AND-circuit 202 which is jointly responsive to STOPand to write resync latch 161 being reset to supply a stop ends countsignal to burst counter 163. The significance of this action is thatAND-circuit 202 detects the CMD OUT being received during the recordingof data; that is, write resync latch 161 is reset. It is desired toimmediately record a check digit. This is accomplished by setting burstcounter 163 to unity for supplying a gateenabled check digit signal overline 167 to OTC 33. This gating is accomplished by the next-occurringwrite clock signal. Immediately after recording the last data signal,STOP is also supplied through OR-circuit 204 to enable AND-circuit 162for incrementing burst counter 163 each time a SET SVC IN signal isreceived over line 190. Circuit 201 supplies a NOT TERMINATE signal overline 213 to enable AND-circuit 162. AND-circuit 192, which is jointlyresponsive to K=1 and NOT STOP cannot now reset steering latch 141.Rather, as soon as write stop latch 151 is set its signal on line 200 issupplied through OR- circuit 205 (FIG. 6) to immediately reset steeringlatch 141. Note that this resetting does not have to wait for a writeclock pulse to be emitted by OTC 33. Upon receipt of the next SET SVC INsignal on line 190, SVC IN latch 191 is set. Again AND-circuit 195 isresponsive to steering

